Sékouba TOURÉ
ELECTRONICS ENGINEER — ANALOG, DIGITAL & RF DESIGN
Electronics and embedded systems engineer with 3 years of hands-on experience at ENVEA, from PCB design and RF/analog circuits to FPGA/VHDL digital systems and full test bench design. Immediately available, open to relocation across France.
Get in TouchWork Experience
ENVEA
Electronics Engineer (Work-Study Program)
Nov 2023 — July 2026- Flagship mission: designing and building test benches for the circuit boards of ENVEA's various analyzers, from requirements gathering through to commissioning — architecture, schematic design, simulation, PCB layout, physical build, validation and technical documentation
- Analog multilayer PCB design and layout under OrCAD (Capture / PCB Editor)
- Complex signal analysis and fault diagnosis (oscilloscope, logic analyzer)
- Integration of hardware interfaces: ADC, GPIO, I2C, SPI and UART
- Functional board validation and test report writing in an industrial environment
Engineering Projects
VHDL Single-Cycle Processor Architecture
32-bit single-cycle processor in VHDL, from the datapath to an interrupt-driven UART peripheral, simulated in ModelSim and implemented on FPGA.
- VHDL
- ModelSim
- Quartus
- FPGA (DE1-SOC)
- UART
- Interrupts (VIC)
2D Radar on SoC-FPGA
Full 2D radar on DE10-Lite: ultrasonic rangefinder and servo motor driven by a Nios II over the Avalon bus, with the scanned map displayed on VGA and exported over UART.
- VHDL
- Nios II
- SoC-FPGA
- Avalon
- Quartus
- ModelSim
- VGA
- UART
- NeoPixel
Technical Stack & Laboratory
EDA & PCB Design
FPGA & Digital Design
Lab Instrumentation & Testing
Languages & Embedded Systems
Tools & Methodologies
About Me
Graduate engineer from Polytech Sorbonne (specializing in Electronics and Embedded Systems, Class of 2026), backed by 3 years of hands-on industrial experience at ENVEA alongside thorough technical training. My expertise centers on analog hardware design, laboratory test bench validation, and digital RTL engineering on FPGA platforms.
My approach is field-driven and practical: understand the system need, design the hardware architecture, route, prototype, and qualify rigorously on the bench. Beyond theoretical concepts, technical competence is proven through physical facts: the reliability of delivered hardware, systematic debugging, and the ability to solve complex real-world issues.
Education: Master of Engineering (Diplôme d'Ingénieur) in Electronics & Embedded Systems — Polytech Sorbonne (2026).
Core Expertise
- Analog & Power Architecture: Low-noise acquisition front-ends, sensor conditioning, active/passive filtering, precision op-amps, power regulation (LDO, DC-DC buck/boost), battery management, and shunt current sensing.
- Test Bench Engineering & Metrology: Turnkey hardware design of automated test fixtures for industrial electronic boards (specifications to qualification), ripple voltage analysis, thermal qualification, and systematic board bring-up.
- High-Density PCB Engineering: Multilayer board design, stackup definition, return path & ground plane integrity, power distribution network (PDN) decoupling, and EMC/ESD hardening.
- Digital & SoC System Design: RTL architecture design, custom CPU datapaths (ALU, register files, pipelining, vectored interrupt controllers), Avalon/memory-mapped bus interconnects, and cycle-accurate simulation.
- RF & Microwave Engineering: S-parameter characterization (VNA), transmission lines & microstrip matching networks, lumped/distributed RF filters, microwave link budgets, and antenna verification.
- Hardware System Interfacing: Bus timing closure, mixed-signal data conversion (high-resolution ADC/DAC), signal integrity on high-speed traces, and physical bus debug.
Feel free to explore the source code and comprehensive technical documentation of my projects on GitHub.
